1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device incorporating a non-volatile semiconductor memory (such as a ferroelectric memory).
2. Description of the Related Art
Generally, in a semiconductor device incorporating a ferroelectric memory, a voltage supplied via an external power supply pin or a voltage obtained by boosting/stepping down the voltage supplied via the external power supply pin is used as a power supply voltage of the ferroelectric memory. Among the semiconductor devices each incorporating the ferroelectric memory, in an IC card (Integrated Circuit Card), a RFID (Radio Frequency Identification), and so on, a stability capacitance (constituted of a ferroelectric capacitance) is often connected between a power supply pin of the ferroelectric memory and a ground line in order to stabilize the power supply voltage of the ferroelectric memory.
The ferroelectric memory has a failure mode regarding data retention called a retention failure, and hence it needs to be guaranteed to retain write data for a predetermined time or more in a power-on state (state in which the power supply voltage is being supplied) and retain write data for a predetermined time or more in a power-off state (state in which the power supply voltage is not being supplied).
Therefore, in a test process of the semiconductor device incorporating the ferroelectric memory, a screening test for a retention failure when the ferroelectric memory is powered off (power-off retention test) is performed in the following steps. First, predetermined data is written into the ferroelectric memory. Subsequently, the voltage supply from an external testing apparatus to an external power supply pin of the semiconductor device is stopped to stop the supply of the power supply voltage to the ferroelectric memory. Then, in a predetermined time after the supply of the power supply voltage to the ferroelectric memory is stopped, the voltage supply from the external testing apparatus to the external power supply pin of the semiconductor device is resumed to resume the supply of the power supply voltage to the ferroelectric memory. Thereafter, data is read from the ferroelectric memory, and the presence or absence of the retention failure is determined by comparing the read data and the predetermined data.
Moreover, Japanese Unexamined Patent Application Publication No. 2000-299000 discloses a non-volatile semiconductor memory which is configured to be able to supply a voltage obtained by stepping down a power supply voltage to a memory block in addition to the power supply voltage and to ensure reliable data retention even when the memory block is constituted of a ferroelectric memory. Japanese Unexamined Patent Application Publication No. 2004-61114 discloses a self-diagnosis test circuit which can realize a reduction in test time, an improvement in yield, and an increase in test coverage in a test of a semiconductor device.
In the conventional semiconductor device, to stop the supply of the power supply voltage to the ferroelectric memory in the power-off retention test of the ferroelectric memory, the supply of the voltage from the external testing apparatus to the external power supply pin of the semiconductor device needs to be stopped. Therefore, during the power-off retention test of the ferroelectric memory, the supply of the power supply voltage to functional blocks except the ferroelectric memory is also stopped. This causes a problem that during the power-off retention test of the ferroelectric memory, the functional blocks except the memory block cannot be tested, thereby increasing a test time of the semiconductor device.
Further, with the stability capacitance, even if the voltage supply from the external testing apparatus to the external power supply pin of the semiconductor device is stopped to stop the supply of the power supply voltage to the ferroelectric memory in the power-off retention test thereof, the voltage is supplied to the ferroelectric memory only for a time taken for discharging an electric charge accumulated in the stability capacitance. Hence, whit the stability capacitance, it is necessary to lengthen the time for stopping of the voltage supply from the external testing apparatus to the external power supply pin of the semiconductor device by the waiting time for the completion of discharge of the electric charge accumulated in the stability capacitance, which causes a problem of an increase in the test time of the semiconductor device.